As semiconductor devices become more highly integrated the dimensions of devices therein have necessarily decreased. For example, integration density has been increased by decreasing transistor feature sizes, including their gate length and channel length. Decreased channel length can result in a short channel effect, which can increase an off-current threshold of the transistors and can deteriorate refresh characteristics of memory devices having such transistors.
In an attempt to avoid such problems, a method of forming a recess channel in a semiconductor substrate has been introduced to extend the channel length of transistors. A semiconductor device with a conventional recess channel transistor array will now be described.
FIGS. 1A and 1B are cross sectional views of a semiconductor device with a conventional recess channel array transistor.
Referring to FIG. 1A, the semiconductor device includes recess channel transistors 181a and 181b. An active region is defined in a semiconductor substrate 100 by a device isolation region 105. The recess channel transistors 181a and 181b include gates 165a and 165b, respectively, a channel impurity doped region 130, and a threshold voltage (Vth) adjusting impurity doped region 150 in the semiconductor substrate 100. The gates 165a and 165b are formed by filling a recess trench 140 in the semiconductor substrate 100. The channel impurity doped region 130 contacts bottom portions of the gates 165a and 165b. A lightly doped region 175 and a source/drain region 170 are sequentially stacked next to the gates 165a and 165b of the recess transistors 181a and 181b. The lightly doped region 175 is connected to the channel impurity doped region 130.
The widths of gates 165a and 165b are different from each other. For example, as shown in FIGS. 1A-B gate 165b is wider than gate 165a. Therefore, the channel length of gate 165b is longer than that of gate 165a. Gate 165a includes a gate electrode layer 160a and a gate insulating layer 155a. Gate 165b similarly includes a gate electrode layer 160b and a gate insulating layer 155b. The gate insulating layers 155a and 155b are formed on a surface of the recess trench 140 in the semiconductor substrate 100 and on a portion of an upper surface of the semiconductor substrate 100. The gate electrode layers 160a and 160b can be formed from a metal, a doped silicon, or the like. The gate electrode layers 160a and 160b are formed on the gate insulating layers 155a and 155b, respectively, and fill the recess trenches 140 and protrude beyond an upper surface of the semiconductor substrate 100.
The recess transistors 181a and 181b are similar to a flat transistor, except that the channel impurity doped region 130 and the Vth-adjusting impurity doped region 150 are formed much lower in the semiconductor substrate 100 than those in a flat transistor. When a gate voltage that is greater than a threshold voltage is applied to the gates 165a and 165b of the recess transistors 181a and 181b, a recess channel is formed therefrom that has a different shape than the recess channel formed that is formed in the flat transistor. More particularly, the recess channel is formed along the curved lower surfaces of the gates 165a and 165b so that the recess channel has a rounded shape, which increases the effective channel length of the recess transistors 181a and 181b relative to the effective channel length in the flat transistor. The extended effective channel length can improve the static and dynamic refresh characteristics of a memory device that includes such transistors.
However, fabrication of very highly integrated semiconductor devices can necessitate the use of recess trenches with decreased widths and can limit the depth of the recesses used for the gates 165a and 165b formed in the semiconductor substrate 100. Accordingly, an effective length of the recess channel that is formed in the channel impurity doped region 130 can decrease. Use of relatively shallow trenches for the recess transistors 181a and 181b can cause variation in the depth and/or width of the recess of the gates 165a and 165b depending upon their location in the semiconductor 100. Such varying depths and/or widths can affect the length of the recess channels formed around lower portions of the gates 165a and 165b and can also affect the concentration of impurities in the threshold voltage impurity region 150 contacting the gates 165a and 165b. Variation in the recess channel lengths and the impurity concentrations between locations in the substrate 100 can cause the threshold voltage and leakage current to vary between transistors even when the recess transistors 181a and 181b have the same gate length. Accordingly, the refresh characteristics of associated memory cells in a memory device can vary across the substrate 100.
Referring to FIG. 1B, decreased gate length can increase an effect of substrate bias. For example, a ratio of a channel depletion region 190a of the recess transistor 181a formed on an edge of the gate 165a in which an electric field is strong relative to the entire depletion region can be greater than a ratio of a channel depletion region 190b of the recess transistor 181b relative to the entire depletion region. As substrate bias increases, the increase of the threshold voltage of the recess transistor 181a can become greater than that of the recess transistor 181b because the recess transistor 181a has a stronger electric field effect. Accordingly, it may be desirable to avoid any increase of such bias effect in the recess channel transistors 181a and 181b as gate length is decreased.